Consumers continue to demand faster computers. To accelerate software execution speeds, many recent efforts have been directed to increasing instruction throughput in modern processor systems (e.g., using a technique called pipelining). Unlike processor systems that require complete execution of an instruction before fetching a subsequent instruction, processor systems that employ pipelining techniques (i.e., pipelined processor systems) do not wait until the result from a previous operation is written back into a register or main memory before executing a subsequent instruction. While pipeline size (i.e., the number of unfinished instructions that can concurrently occupy the pipeline) may fluctuate depending on the processor architecture, modern processor architectures tend to have longer pipelines than earlier processor architectures.
Although pipeline processors typically execute code in an efficient manner, a problem may occur when a branch instruction is processed or executed. A branch instruction may occur within, for example, an if-then-else construct. When the processor initially executes the instruction(s) associated with the if-then-else construct, the location to which the processor must branch is not yet known. As a result, the processor must wait for instructions in the pipeline to complete execution (e.g., the processor stalls) before the branch operation can be executed. With the increased number of instructions held in a modern processor pipeline, waiting for completion of instructions in the pipeline may result in an unacceptable delay.